Multiplexer in vhdl with structural design

Question

I am totally new to VHDL and I want to implement the following MUX for a logical implication S0 => S1 without using other gates.

I want to use structural design, but one of my main problems is that I don't understand how to map the ports correctly so that I am implementing the given implication.

My code so far is compiling and iSim starts but I get two warnings:

mux41_impl remains a black-box sinse it has no binding entity.
mux_out_test has value U

Furthermore, I understand that my component has to match the entity exactly but if I rename it to the entities name I am getting an illegal recurion message.

code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MUX41_IMPL_top is
port (
    D0, D1, D2, D3, S0, S1: in STD_LOGIC;
    mux_out : out STD_LOGIC
);
end MUX41_IMPL_top;

architecture structure of MUX41_IMPL_top is

component MUX41_IMPL
    port (
        D0, D1, D2, D3, S0, S1: in STD_LOGIC;
        mux_out : out STD_LOGIC
    );
end component;

begin

u1: MUX41_IMPL port map (D0, D1, D2, D3, S0, S1, mux_out);
end structure;

testbench code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MUX41_IMPL_SIMBOX is
end MUX41_IMPL_SIMBOX;

architecture TEST_MUX41_IMPL of MUX41_IMPL_SIMBOX is

component MUX41_IMPL is
    port (
        D0, D1, D2, D3, S0, S1: in STD_LOGIC;
        mux_out : out STD_LOGIC
    );
end component;

signal D0_test : STD_LOGIC := '1';
signal D1_test : STD_LOGIC := '0';
signal D2_test : STD_LOGIC := '1';
signal D3_test : STD_LOGIC := '1';
signal S0_test, S1_test : STD_LOGIC := '0';
signal mux_out_test : STD_LOGIC;

for my_MUX41_IMPL : MUX41_IMPL use entity work.MUX41_IMPL_top(structure);

begin
    my_MUX41_IMPL : MUX41_IMPL
    port map (
    D0 => D0_test,
    D1 => D1_test,
    D2 => D2_test,
    D3 => D3_test,
    S0 => S0_test,
    S1 => S1_test,
    mux_out => mux_out_test
    );

    S0_test <= not S0_test after 2 ns;
    S1_test <= not S1_test after 4 ns;

end TEST_MUX41_IMPL;

WARNING:HDLCompiler: - "mux41_impl" remains a black-box since it has no binding entity. It's a warning because components are not required to be bound. Where is the entity and architecture for MUX41_IMPL? Without those found in a reference library (which can be work) the instance won't be bound. Why is MUX41_IMPL_top shown here? It's not used. — , May 08 '20 at 16:43
Where is `MUX41_IMPL` defined? When you say _I want to implement the following MUX_ do you perhaps mean to say _I want to __use__ the following MUX_? — rtx13, May 09 '20 at 17:52
@rtx13 in the code section, not the textbench there is the `MUX41_IMPL_top` entity. This is my 4:1 MUX entity. @user1155120 I renamed this to MUX41_IMPL_top because i got a recursion if it is named like the component itself. — Landau, May 09 '20 at 19:00
@rtx13 and yes I want to use this MUX to implement the logical implication "S0 => S1". just by using structural design :) — Landau, May 09 '20 at 19:06
I'm still not sure I follow. `MUX41_IMPL_SIMBOX(TEST_MUX41_IMPL)` uses `MUX41_IMPL_top(structure)`. In turn, `MUX41_IMPL_top(structure)` uses `MUX41_IMPL`. Where is `MUX41_IMPL` defined? In other words, where is the (non-structural) RTL for `MUX41_IMPL`? — rtx13, May 09 '20 at 22:36

score 1 · Accepted Answer · edited Jun 07 '20 at 06:34

entity MUX41_IMPL_top is
port (
    D0, D1, D2, D3: in STD_LOGIC;
    Sel : in std_logic_vector(1 downto 0);    
    mux_out : out STD_LOGIC

);
end MUX41_IMPL_top;

architecture structure of MUX41_IMPL_top is
begin

with Sel select
    mux_out <=  D0 when "00",
                D1 when "01",
                D2 when "10",            
                D3 when "11",            
                '0' when others;    

architecture structure;

Multiplexer in vhdl with structural design

1 Answers1