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I am trying to understand how c2 compiler in hotspot jvm translate memory barriers for load/store of volatile variables to assembly code.

I understand that for x86 to add StoreLoad barrier, the interpreter will add lock; addl $0,0(%%esp) to the assembly code. So what about c2 compiler? I know c2 operates on Ideal Graph (IR), and adds appropriate barrier nodes before and after load/store nodes (for volatile variables). Do they use lock as in the interpreter mode, or use fence instructions (LFENCE, SFENCE and MFENCE)? Is the code for barriers emitted in compiler mode the same with interpreter mode? Can I refer to some translation rules or manually check them?

Peter Cordes
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Binhaoo
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    lfence and sfence are useless (except for sfence after NT stores), and `lock addl $0, (%esp)` is just another way to do what `mfence` does (more efficiently on some CPUs) [Does lock xchg have the same behavior as mfence?](https://stackoverflow.com/q/40409297). But ESP instead of RSP? Do you care about 32-bit code? And yes, you can check HotSpot's final optimized asm: [How to see JIT-compiled code in JVM?](https://stackoverflow.com/q/1503479). – Peter Cordes Mar 12 '20 at 07:28
  • You might find something about where in the HotSpot sources to look for how it JITs in [Where is the assembly implementation code of the intrinsic method in Java HotSpot?](https://stackoverflow.com/q/48198982) - that's about JITing a specific intrinsic. – Peter Cordes Mar 12 '20 at 07:29
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    Does this answer your question? [How to see JIT-compiled code in JVM?](https://stackoverflow.com/questions/1503479/how-to-see-jit-compiled-code-in-jvm) (edit: bleh, not used to *not* having a gold badge in any of the tags of a question like this; I only added x86 myself so it doesn't count for duphammering) – Peter Cordes Mar 12 '20 at 07:29
  • [Why is (or isn't?) SFENCE + LFENCE equivalent to MFENCE?](https://stackoverflow.com/q/27627969) explains why LFENCE and SFENCE are irrelevant; unless you're using NT stores, regular loads/stores already have ordering that strong. And you can't combine them to build an MFENCE full barrier. [Does the Intel Memory Model make SFENCE and LFENCE redundant?](https://stackoverflow.com/q/32705169) – Peter Cordes Mar 12 '20 at 07:34
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    Thanks! I understood that the compiler uses `lock` instead of `MFENCE` for memory barriers. I have checked the assembly code dumped by PrintAssembly flag and found the lock instructions. – Binhaoo Mar 12 '20 at 20:25
  • You could post an answer to your own question if you want. Feel free to summarize or copy my comments and/or links if you want. – Peter Cordes Mar 12 '20 at 20:29

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