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I've been assembling (and disassembling) the BSWAP x64 instruction with both NASM and GAS, and both assemble the instruction BSWAP r15 as 490FCF in hex. Disassemblers also disassemble this to the same instruction.

The REX prefix for the instruction (49) thus has the REX.W bit (bit 3) and the REX.B bit (bit 0) set. This is directly in contrast to the Intel documentation, which states:

In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits.

(Emphasis mine)

So according to the documentation, the REX.W bit and the REX.R bit (bit 2) should be set, not REX.B, giving the encoding 4C0FCF.

My question is, who is correct? The assemblers or Intel?

owacoder
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  • The manual is wrong there. See _"Figure 2-7. Register Operand Coded in Opcode Byte; REX.X & REX.R Not Used"_. – Jester Nov 26 '18 at 15:48
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    Ahh, missed that. But it makes you wonder why they would use REX.B over REX.R for in-opcode encoding. REX.R makes more semantic sense. – owacoder Nov 26 '18 at 15:50

1 Answers1

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The manual is wrong there. See the description of the REX prefix in section 2.2.1.2 More on REX Prefix Fields instead which says:

REX.B either modifies the base in the ModR/M r/m field or SIB base field; or it modifies the opcode reg field used for accessing GPRs.

and Figure 2-7. Register Operand Coded in Opcode Byte; REX.X & REX.R Not Used which looks like:

Figure 2-7. Register Operand Coded in Opcode Byte; REX.X & REX.R Not Used

The BSWAP uses an opcode reg field.

Jester
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