Reducing number of constraints in R1CS from an arithmetic circuit

Question

The article Ligero++ (https://dl.acm.org/doi/pdf/10.1145/3372297.3417893) says "The number of constraints in R1CS maps to the number of multiplication gates in arithmetic circuits." But I understand the basic way to map an arithmetic circuit to R1CS will also map additions as constraints as shown in Vitalik Buterin's blog post (https://medium.com/@VitalikButerin/quadratic-arithmetic-programs-from-zero-to-hero-f6d558cea649). Is there a way to map a circuit containing addition and multiplication gates to R1CS such that the number of constraints is the number of multiplication gates?

Answer 1

@lamba is already aware of this, but I thought I'd add a response for future reference as there is not a lot of resources on this.

R1CS is a language which asks for an input $v$ such that $$Av\circ Bv = Cv$$ Where $\circ$ is coordinate-wise product, for a given set of matrices $A,B,C$.

Essentially, each row of a R1CS will encode: linear equation * linear equation = linear equation. So this allows for much greater optimisation than naively converting each multiplication and addition into a single row. For instance, suppose you wish to check the following equation holds: $$ax(by+cz) = dx + ey + fz + g$$

With constants $a,b,c,d,e,f,g$ and inputs $x,y,z$.

If we let $v = (1,x,y,z)^T$, we can represent the equation above in R1CS as follows:

$$A = (0,a,0,0), B=(0,0,b,c), C =(g,d,e,f)$$

So rather than getting a constraint for every addition and multiplication - which would be ~11 constraints, we can do it with just one.