What does the expression mean(^bus === 1'bX) in verilog?

Question

I was finding a way to detect any x or z present in input so I find out this (^bus === 1'bX) but I am unable to interpret it. How are we able to detect x or z using this expression and with whom are we doing the xor of bus?

Answer 1

The left side ^bus is unary reduction xor operator. For example, if bus is three bits wide, ^bus is equivalent to bus[0] ^ bus[1] ^ bus[2]. If any of the bits is X or Z, it is propagated to the result.

The right side 1'bX is a 1-bit wide literal that has all bits set to X.

The operator === compares the sides, including equality of X and Z states.