You can use the report statement.
If you declared the status of your simulation as:
signal simulation_status : std_logic;
Then you can use:
report "simulation status = " & std_logic'image(simulation_status);
Of course, you want to wait until the end of the simulation before reporting the status, in your testbench you can create an apposite process to do so:
process
begin
wait for 1000 ns; -- until the end of your simulation
report "simulation status = " & std_logic'image(simulation_status);
wait;
end process;
By default report has severity note, but you can also use warning, error and failure, for example:
report "simulation status = " & std_logic'image(simulation_status) severity failure;
When a report with severity failure is reached, it will stop the simulation.