Consider this example from Wikipedia:
P1 | W(x)1
----------------------------------
P2 | R(x)1 W(x)2
----------------------------------
P3 | R(x)2 R(x)1
----------------------------------
P4 | R(x)1 R(x)2
Where P1 - P4 are different processors that issue read and write instructions to variable x in the given orders (their written and read values are given as well). It is clear that this example is Processor Consistent so it must also be Cache Coherent. But how is this possible in this example?
