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For example, if it takes 1 cycle to read the cache and 3 cycles to write the cache, is the hit time equal to 4 cycles? Also, does this vary based on whether the cache is an instruction cache or a data cache?

LuminousStar
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2 Answers2

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I would say, it depends.

Overall there are several strategies how a cache could be incorporated into a process. Few of these options are:

  • read through: a client reads from cache, and if the cache does not have a value, then the cache itself reads the data from the store. And the cache saves the value before being returned to a customer. In this case the cost will be vary, depending if the value is already in cache.
  • cache aside is another option - the client checks the cache - the cache either gives back the value or returns nothing. If the value was not found, it's the client who goes to datastore to read and also write to the cache.

There are few more strategies, and all of them will have a different cost.

Also, it is important to understand what "cache hit" and "cache miss" is. These are term unrelated to the way how cache is integrated. By definition, a cache hit happens when a client requests a key, and the key is already in the cache, regardless how that key got there. "Cache miss" is opposite - a client asks for the key, and the key is not there.

AndrewR
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The definition of cache hit time [Patterson2018, pp. 368, last paragraph and on the left column] is: "The time required to access a level of the memory hierarchy, including the time needed to determine whether the access is a hit or a miss."

Hence, it does not include the time to write to a location in a cache. It only includes the time to read a location in the cache.

By definition, there is no difference between data cache and instruction cache for this definition.

@book{Patterson2018,
    Address = {Cambridge, {MA}},
    Author = {David A. Patterson and John L. Hennessy and Andrew S. Waterman and Yunsup Lee and Perry Alexander and Peter J. Ashenden and Jason D. Bakos and Javier Diaz Bruguera and Jichuan Chang and Matthew Farrens and David Kaeli and Nicole Kaiyan and David Kirk and Zachary Kurmas and James R. Larus and Jacob Leverich and Kevin Lim and Eric Love and John Nickolls and John Y. Oliver and Milos Prvulovic and Partha Ranganathan and Mark Smotherman},
    Edition = {{RISC-V}},
    Publisher = {Morgan Kaufmann},
    Series = {The Morgan Kaufmann Series in Computer Architecture and Design},
    Title = {Computer Organization and Design: The Hardware/Software Interface},
    Year = {2018}}
Giovanni
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